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Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array – Logic array for general logic functions – 10,000 to 100,000 typical gates (see – Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity) Cost-efficient programmable architecture for high-volume – Low cost solution for high-performance communications TM I/O pins can drive or be driven by 2.5-V, 3.3-V, or – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) for 3.3-V operation at 33 MHz or 66 MHz (this posting is the responsibility of the poster) |
Myrtle.lowe@dfwind.com (Myrtle Lowe) for more information. All emails will be forwarded to the poster's actual email address.