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Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset Inputs Are TTL-Voltage Compatible. Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption. Balanced Propagation Delays. ±24-mA Output Drive Current. Fanout to 15 F Devices. SCR-Latchup-Resistant CMOS Process and Circuit Design. Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015.srface mount smd ssurface mount (this posting is the responsibility of the poster) |
V_gaines@dfwind.com (Virgil Gaines) for more information. All emails will be forwarded to the poster's actual email address.
